1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a capacitor electrode of a semiconductor memory device.
2. Description of the Prior Art
Of semiconductor memory devices, there is a DRAM in and from which storage information can be arbitrarily input and output. In this DRAM, a memory cell constituted by one transfer transistor and one capacitor has a simple structure, so that this memory cell is widely used as one most suitable for high integration of semiconductor memory devices.
With higher integration of semiconductor devices, a capacitor having a three-dimensional structure has been developed and used for this memory cell due to the following reason. With micropatterning and an increase in density of a semiconductor element, a reduction in occupied area of a capacitor is indispensable. However, to assure the stable operation and reliability of a DRAM, a predetermined capacitance value or more is required. For this purpose, the structure of a capacitor electrode must be changed from a two-dimensional one to a three-dimensional one, thereby increasing the surface area of the capacitor electrode within a reduced occupied area.
The three-dimensional structure of the capacitor in the memory cell of the DRAM includes a stacked structure and a trenched structure. Although these structures have both merits and demerits, respectively, a capacitor having a stacked structure has a high resistance to incident .alpha.-rays or noise from, e.g., a circuit and stably operates even with a relatively small capacitance value. For this reason, the capacitor having the stacked structure is considered to be effective in a 1-gigabit DRAM in which a semiconductor element is designed on the order of about 0.15 .mu.m.
As the capacitor having the stacked structure (to be referred to as a stacked capacitor hereinafter), fin-like capacitors and cylindrical capacitors are proposed. For example, the paper entitled "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS" is contributed to INTERNATIONAL ELECTRON DEVICES MEETING, 1988, PP. 593-595, or Japanese Unexamined Patent Publication No. 1-270344 has proposed a fin-like structure of a capacitor electrode to increase the surface area of the information storage electrode of the capacitor. In addition, Japanese Unexamined Patent Publications Nos. 3-232271 and 6-29463 has made proposals in which the information storage electrodes of capacitors are formed into cylindrical structures to increase the surface areas.
A process common to the major steps of forming capacitor electrodes having three-dimensional structures such as a fin-like structure and a cylindrical structure is that a silicon oxide film (spacer film) and a material film serving as an information storage electrode are stacked and dry-etched, and then the silicon oxide film (spacer film) used to shape the information storage electrode of this capacitor is etched and removed by using a chemical solution of a hydrogen fluoride solution.
To prevent etching of an insulating interlayer below the capacitor electrode, an insulating-interlayer etching prevention layer (stopper film) must be formed between the insulating interlayer and the capacitor electrode, and particularly, the information storage electrode by using a material having an etching selectivity ratio to the silicon oxide film (spacer film). At present, a silicon nitride film whose etching rate is about 1/100 of that of a silicon oxide film in use of a hydrogen fluoride solution is widely used as this stopper film.
A method of forming a conventional capacitor electrode will be described below with reference to the accompanying drawings. FIGS. 1A and 1B are sectional views showing the major steps of a cylindrical electrode, respectively.
As schematically shown in FIG. 1A, a field oxide film 22 serving as an element isolation insulating film is formed on the surface of a silicon substrate 21. A gate electrode 23 which constitutes the transfer transistor of a memory cell, and a diffusion layer 24 for a capacitor and a diffusion layer 25 for a bit line which respectively serve as the source and drain regions are formed. A word line 23a is formed on the field oxide film 22. An insulating film 26a for covering the gate electrode 23 and the word line 23a is formed of a silicon oxide film or the like. A bit-line contact plug 27a is formed on the above-described diffusion layer 25 for a bit line. A bit line 27b electrically connected to the bit-line contact plug 27a is disposed, and an insulating interlayer 26b for covering the bit line 27b is deposited.
A stopper film 28 which is stacked on the insulating interlayer 26b is formed. The stopper film 28 consists of a silicon nitride film.
Then, a contact hole is formed above the above-described diffusion layer 24 for a capacitor to form a structure, as shown in FIG. 1A, which is constituted by first and second silicon films 29 and 30 serving as the information storage electrode of the capacitor and containing a phosphorus impurity, and a spacer film 31 for shaping the information storage electrode.
The spacer film 31 is selectively etched and removed with a hydrogen fluoride solution to form the information storage electrode of the capacitor, as shown in FIG. 1B.
In this manner, the gate electrode 23 of the transfer transistor, the diffusion layer 24 for a capacitor and the diffusion layer 25 for a bit line which serve as the source and drain regions, the first and second silicon films 29 and 30 which are electrically connected to the diffusion layer 24 for a capacitor and serve as the information storage electrode, and the bit line 27b electrically connected to the diffusion layer 25 for a bit line through the bit-line contact plug 27a are formed in an active region other than the field oxide film 22 on the surface of the silicon substrate 21. The first silicon film 29 is buried in the contact hole formed in the insulating interlayers 26a and 26b and the stopper film 28, and covers the surface of the stopper film 28.
When a fin-like capacitor electrode is to be formed, silicon films serving as capacitor electrodes, and spacer films as silicon oxide films for shaping the capacitor electrodes are deposited to be alternately stacked on a stopper film serving as an insulating-interlayer etching prevention layer and consisting of a silicon nitride film. These films are patterned by dry etching. Thereafter, only the spacer films are selectively etched and removed with a hydrogen fluoride solution to form the information storage electrodes of the capacitor.
When, however, the silicon nitride film is used as the insulating-interlayer etching prevention layer (stopper film), the insulating interlayer and the silicon nitride film frequently crack due to a heavy stress from the silicon nitride film, interfering with the process of manufacturing a semiconductor device. Further, since the silicon nitride film is an insulating film having a high trap density, the semiconductor device is charged up, adversely affecting its operation. In addition, since this silicon nitride film has a large blocking force with respect to permeation of hydrogen gas, annealing with hydrogen gas, which is indispensable for stabilizing the operation of the semiconductor device, cannot be sufficiently performed. As a result, the reliability and yield of the semiconductor device are reduced.
To avoid this situation, a method of decreasing the thickness of the silicon nitride film may be conceivable. However, the selectivity ratio of the silicon nitride film to the silicon oxide film is about 100:1, so that the silicon nitride film requires a film thickness of several tens nm or more. Therefore, it is difficult to decrease the thickness of the silicon nitride film to a degree enough to reduce the adverse effect.